The integrated circuit industry has a long history of “Moore's law” scaling of silicon transistors from dimensions of over 10 microns to today's 22 nm generation. In the current 22 nm generation the industry has moved to a FinFET or tri-gate structure in which the gate is wrapped around three sides of the silicon channel to provide improved electrostatic control of the carriers.
While further scaling is proceeding, the channel in the latest Intel tri-gate transistor is only about 20 atoms wide, so the end to scaling is clearly on the horizon. The industry has identified several directions for continuing the evolution of CMOS circuits. One direction that is being actively investigated is the use of higher mobility materials such as III-V semiconductors, III-N materials and Ge for the transistor channel. Another alternative is the use of vertical transistors with wrap-around (gate all around) geometries, again all of the same material classes are being investigated.
This evolution to heterostructure transistor structures requires new manufacturing approaches. Two principle directions are being investigated: wafer bonding; and heterostructure materials growth. In wafer bonding, the non-silicon materials are grown on their conventional substrates with the inclusion of a separation layer. Following the growth, the epitaxial material is bonded to a silicon wafer and selective etching is used to separate the original substrate. Films of only a few nm thickness have been transferred with this approach. Since the non-silicon material is grown using well established technologies, the issues of lattice mismatch and defects are largely controlled. However, this is a complex technology and is far from manufacturing worthy for the large area silicon substrates (today 300 nm diameter migrating to 450 nm diameter) used by the silicon integrated circuit industry. Thermal expansion mismatch issues (the expansion coefficients of the III-V materials and the Si substrate are different) remain.
Heteroepitaxial growth of different semiconductor and dielectric materials directly on Si(001) is another approach. The main issues are defects associated with the lattice and thermal expansion mismatches between the foreign material and the Si. For large area growths, these issues give rise to dislocations and can cause cracking of the foreign film. Traditionally a thick buffer layer is grown to mitigate these effects and reduce the defects between the substrate and the active layer. While there has been some success with this approach, it is not compatible with integration on the very small scales of today's silicon integrated circuits.